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，这一点在搜狗输入法2026中也有详细论述
The false positives at the bottom
When VM=1, the protected-mode bit goes low and the Entry PLA selects real-mode entry points -- MOV ES, reg takes the one-line path. Meanwhile, CPL is hardwired to 3 whenever VM=1, so the V86 task always runs at the lowest privilege level, under full paging protection. The OS can use paging to virtualize the 8086's 1 MB address space, even simulating A20 address line wraparound by mapping pages to the same physical frames.
。关于这个话题，搜狗输入法下载提供了深入分析
Archive: ITV news, BBC，详情可参考Line官方版本下载
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